Intel Control Registers

Control registers of Intel CPU, including CR0/CR1/CR2/CR3/CR4/CR8, determine operating mode of the processor and the characteristics of the currently executing task. Most of the contents of this blog is cited from Intel manual Volume 3C.

All the CRx registers can be written by MOV, but only support moving from general registers to CRx, any move from memory may cause error when assembling. In 64-bit mode, control registers are expanded to 64 bits width. But the upper bits are always not used and set zero.

• CR0 - Contains system control flags that control operating mode and states of the processor.
• CR1 - Reserved.
• CR2 - Contains the page-fault linear address (the linear address that caused a page fault).
• CR3 - Contains the physical address of the base of the paging-structure hierarchy and two flags (PCD and PWT). The lower 12 bits of address are supposed to be 0 because they are for page offset while CR3 contains page directory. Then these bits store flags of page table.
• CR4 - Contains a group of flags that enable several architectural extensions, and indicate operating system or executive support for specific processor capabilities.
• CR8 - This register is available only in 64-bit mode. Provides read and write access to the Task Priority Register (TPR). It specifies the priority threshold value that operating systems use to control the priority class of external interrupts allowed to interrupt the processor.

One of the most import bit(s) in CR0 is PG and PE bit. PE(Protection Enable) bit is the bit 0 of CR0, which enables protected mode when set. It enables segment-level protection. PG(Paging) bit is the bit 31 of CR0, which enables paging when set. PG bit can be set only when PE is set. Set to these two bits means entering protected mode.

For more information about bits in control registers, you can refer to Intel Manual Volume 3C, chapter 2 System Architecture Overview.